The present invention relates to semiconductor integrated circuits (ICs), and more particularly to a low-voltage programmable element that can be used in the implementation of one-time programmable memory storage as well as in other high-density applications.
In the semiconductor industry, it is oftentimes desirable to fabricate a very large-scale integrated (VLSI) circuit which includes a one-time programmable (OTP) non-volatile memory element that can be programmed either during wafer probing or after packaging of the semiconductor die. For example, programming of an OTP non-volatile memory element is used to provide self-contained identification information about an individual IC die or die revision. OTP non-volatile memory can also be used for remapping addresses of defective DRAM (dynamic random access memory) cells so that functional redundant memory cells are addressed instead. OTP non-volatile memory may also provide hard-coded digital trimming data for precision analog elements.
There are several different methods known in the art to implement non-volatile data storage on an IC die. In one method, metallic fuses can be selectively programmed by exceeding a certain current and thereby creating an open circuit in the fuse. This changes the resistance of the metallic fuse from an initial low-resistance to a high-programmed resistance.
In another method, antifuses are selectively programmed by applying a relatively high-programming voltage to break down a dielectric material contacted by two conductive terminals of the antifuse. This permanently changes the resistance presented by the antifuse from a high initial resistance to a low-programmed resistance. The programmed resistance obtained is typically on the order of several 1000 ohms.
In accessing the antifuse for a read operation, the programmed resistance is used, for example, to couple the input capacitance of a logic gate to a high logic level provided by a power supply, or, alternatively, to a low logic level provided by a connection to ground. The time required to charge or discharge the input capacitance of the logic gate is proportional to the product of the programmed resistance of the fuse and the input capacitance of the logic gate.
The required programming voltage of prior art fuses and antifuses to implement OTP non-volatile memory storage is quite high (on the order of 10-12 volts) and oftentimes the high-programming voltages must be routed to other circuits in the IC which are not typically capable of withstanding such high voltages. Moreover, the introduction of high-voltage programmable fuses and antifuses into an IC die may require some redesigns and process modifications in order to avoid damage to the IC die. In some instances, extra processing steps are needed which increase the overall production cost of the IC die. In addition to requiring high-programming voltages, prior art fuses and antifuses occupy a large space on the IC die which detracts from the space were other ICs devices can be formed.
In view of the drawbacks with prior art OTP elements, there is a need for providing a new and improved OTP element that can be programmed using voltages that are less than about 5 V. Moreover, there is a need for providing a low-cost alternative OTP element that can be used for other high-density applications including electronic fuses, field programmable logic devices, encryption coded macros or systems, ROMs, etc.
One object of the present invention is to provide a programmable element which can be used in the implementation of OTP memory storage as well as other high-density applications such as electronic fuses, field programmable logic devices, encryption coded systems or macros, and ROM.
Another object of the present invention is to provide a programmable element which can be programmed using relatively low-programming voltages as compared with the programming voltages that are typically required to program conventional OTP elements such as fuses and antifuses.
A still further object of the present invention is to provide a programmable element which can be fabricated using existing CMOS (Complementary Metal Oxide Semiconductor) fabrication techniques without the need of using extraneous processing steps.
An even further object of the present invention is to provide a programmable element which can be formed in a relatively small space on a surface of an IC die.
These and other objects and advantages are achieved in the present invention by providing a FET as the programmable element in which the source/drain regions are not present beneath the gate region of the FET. This so-called xe2x80x9cunderlappedxe2x80x9d FET device is formed at the same time as the other FET devices of the IC are formed except that a block mask is used to prevent the implantation of source/drain extension regions therein.
Because the inventive underlapped FET device does not include extension implants therein, the inventive underlapped FET device has a higher source-to-drain resistance than most of the other types of FET devices that are present in the IC. The exclusion of the extension implants permits the inventive underlapped FET device to be used as a low-voltage OTP element for those other types of FETs.
Specifically, one aspect of the present invention relates to an integrated circuit chip which comprises a first set of field effect transistors (FETs) having a first source-to-drain resistance and a second set of FETs having underlapped source/drain regions and a second source-to-drain resistance, wherein said second source-to-drain resistance is at least 50% greater than said first source-to-drain resistance and said second set of FETs is programmable.
A further aspect of the present invention relates to an integrated circuit chip which comprises a first set of transistor logic devices that operate at a first supply voltage, a second set of transistor input/output (I/O) devices that operate at a second supply voltage that is greater than the first supply voltage, and a third set of transistor programmable devices that are programmed at said second supply voltage.
The present invention also provides a programmable field effect transistor (FET) device that comprises source and drain elements which are separated by a channel region, and a gate region present atop a portion of said channel region, said source and drain elements are not located beneath said gate region, wherein during programming charge is trapped outside of the channel region.